This invention relates to floating point arithmetic units and, more particularly, to an apparatus for computing a sticky bit for the arithmetic unit.
When numeric operands are represented in the form A.sup.x, B.sup.y within a computing system, the exponents x and y must be the same when two numbers are to be added or subtracted. If the exponents differ, the binary representation of the mantissa of the number having the smaller exponent must be shifted by an amount equal to the difference between the two exponents. FIG. 1 is a shift control circuit 10, not necessarily in the prior art, which performs such shifting. Shift control circuit 10 includes subtractors 14 and 18 which receive the operand exponents, designated exp (A) and exp (B), over buses 22 and 26. Subtractor 14 performs the operation exp (A)-exp (B), and subtractor 18 performs the operation exp (B)-exp (A). The resulting data in the form of shift counts from subtractors 14 and 18 are communicated to selection logic 30 over buses 34 and 38. Selection logic 30 determines which exponent is larger (e.g., by determining which shift count is positive or negative) and communicates a selection signal to a multiplexer 42 over a bus 44. Selection logic 30 communicates the positive shift count to a shift circuit 46 over a bus 50. Multiplexer 42 receives the operand mantissa designated mantissa (A) and mantissa (B), over buses 54 and 58, respectively. Multiplexer 42 selects the mantissa to be shifted in response to the selection signal received over bus 44 and communicates the selected mantissa to shift circuit 46 over a bus 62. Shift circuit 46 shifts the selected mantissa by an amount equal to the shift count received over bus 50. The shifted mantissa then is communicated to an ALU over a bus 66.
The number of bits used to represent the mantissa depends upon the precision mode selected in the particular computer. In single precision mode, each mantissa is represented with 24 bits, whereas in double precision mode each mantissa is represented with 53 bits. Since arithmetic operations in both single and double precision mode are processed the same way, only double precision mode shall be discussed herein.
FIG. 2A is a diagram of a double precision mantissa register 70. Mantissa register 70 includes fifty-three storage locations labeled B01-B53. B53 is always 1 if denormal numbers are not supported. The programmer uses these storage locations to store the binary representation of the mantissa for use by multiplexer 42. FIG. 2B is a diagram of a double precision mantissa register 72 which may be used to store the shifted mantissa before it is communicated to the ALU. Mantissa register 72 includes fifty-three storage locations S01-S53 which are used to store the shifted mantissa. Additionally, mantissa register 72 includes three storage locations which are transparent to the programmer. These storage locations comprise a guard bit (G), a round bit (R), and a sticky bit (S) as specified by the standard IEEE 754. The guard and round bits are the first and second bits beyond rounding precision. The sticky bit (S) indicates whether or not a nonzero value in bit positions B01-B53 of mantissa register 70 was shifted out during the mantissa shifting operation. A sticky bit value of "1" indicates that a meaningful portion of the mantissa has been lost and that the result of the mathematical operation may be inaccurate. Thus, calculation and monitoring of the sticky bit is very important to conform to the standard.
One approach used to calculate the sticky bit, not necessarily in the prior art, is shown in FIG. 3. The shift count from selection logic 30 is used to generate a mask 74 which is logically ANDed to the mantissa to be shifted which is stored in register 70. The mask typically contains a "1" in the number of least significant bit positions corresponding to the shift count (e.g., if the shift count equals five, the five least significant bit positions will contain a "1"). The result of the logical AND operation is stored in a register 82. Each storage location in register 82 which contains a "1" indicates that a corresponding nonzero bit in register 70 will be lost after the shifting operation. Thereafter, a logical OR is performed on each bit in register 82 to produce the sticky bit. Thus, if at least one nonzero bit in the mantissa will be lost as a result of the shifting operation (e.g., bits B04 and B03 in register 78), then that event will be indicated by a sticky bit equal to 1. Because of hardware constraints in the calculation of the shift count, the mask pattern cannot be generated until almost all bits of the outputs of subtractors 14 and 18 are available.
A second approach to sticky bit calculation is to logically OR the actual bits that are shifted out beyond the guard and round bit positions as shifting takes place. In this approach, the final sticky bit cannot be computed until all the shifting steps are finished.
With either approach, calculation of the sticky bit ordinarily lies in a critical path in the overall arithmetic sequence, and the arithmetic operation cannot proceed until the sticky bit is available.